Chip Morphing Abstract


Engineering is a study of tradeoffs. In computer engineering the tradeoff has traditionally been between performance, measured in instructions per second, and price. Because of fabrication technology, price is closely related to chip size and transistor count. With the emergence of embedded systems, a new tradeoff has become the focus of design. This new tradeoff is between performance and power or energy consumption. The computational requirements of early embedded systems were generally more modest, and so the performance-power tradeoff tended to be weighted towards power. “High performance” and “energy efficient” were generally opposing concepts.

However, new classes of embedded applications are emerging which not only have significant energy constraints, but also require considerable computational resources. Devices such as space rovers, cell phones, automotive control systems, and portable consumer electronics all require or can benefit from high-performance processors. The future generations of such devices should continue this trend.


Traditionally, performance has been improved by increasing the complexity of a micro-architecture. Unfortunately, power reduction has traditionally been accomplished by reducing processor complexity. Resolving these opposing demands is the primary challenge for low power high performance architectures.

This growth in processor complexity is clearly demonstrated by the growth in the number of transistors in a processor. This complexity has taken many forms, such as multiple levels of cache, multiple functional units, and out of order execution. Though these techniques increase performance, they expend energy and experience diminishing returns. Indeed, it would appear that complex superscalar designs inherently contain too much overhead to be energy efficient.


Three key ratios are the focus to high-performance and low-power processor design: instructions per cycle (IPC), energy per instruction (EPI), and energy per cycle (EPC). These metrics can determine if a processor can provide high-performance, if it can do so in a power efficient manner, and if it dissipates little power even when high-performance is not required.

IPC is the first level estimate of architectural speed. If a processor does not contain any features which would inherently limit the clock speed, IPC can provide a good estimate of actual performance. If power consumption were not an issue, then IPC would be the primary metric. EPI gives the most direct measure of energy efficiency. For embedded applications, energy measurement is generally more useful than power estimation because embedded applications are more likely to be constrained by a battery. A suite of applications that must be run cannot consume more total energy than is stored.

Chip Morphing Seminar Abstract

Because these embedded applications show large fluctuations in their performance requirements, the tradeoff between performance and power can change. Thus, we need an additional metric for when power consumption is less important than performance, such as ’standby’ modes found in many portable telecommunications devices. EPC provides such a metric, as it discards performance concerns and allows focus just on the energy consumed over time.

The Multi-Cluster Micro Architecture

In both cases, a relatively conventional shared fetch and decode unit fetches blocks of instructions, and determines what class of instructions they are (any branch prediction is done here). The differences between the two begin here, however. In the conventional design, a Register Renaming unit, keeps track of the mapping between architectural registers assumed by the program and the physical registers allocated to them in the common register file. In the conventional design, the new instructions are added to a common issue window, and extracted as dependencies are solved. The single common multi-ported register file holds all the physical registers.


This paper has attempted to introduce the main concepts in the Morph project, an attempt to approach low power embedded system in a novel way - by attacking power consumption during those frequent times when less than peak performance is needed.